AD9957SLASHPCBZ datasheet(44/62 Pages) AD

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Data Sheet

AD9957

Rev. E | Page 43 of 61

Logic 0 state. To reset the validation result latch when the sync

receiver is active, however, requires the use of the Sync Timing

Validation Disable bit in the multichip sync register. To make a

setup/hold validation measurement is a two-step process. First,

write a Logic 1 to the sync timing validation disable bit. Then,

to make a measurement, write a Logic 0. The first action resets

the validation result latch and holds it in a reset state; the

second action releases the reset state and enables the validation

result latch to capture a setup/hold validation measurement.

Each time a new setup/hold validation check is desired, this

two-step procedure must be performed.

Because the programmed value of the sync validation delay

establishes the time window for a setup/hold measurement,

the amount of delay is an important consideration for proper

operation of the validation block. The value chosen should

represent a small fraction of the SYSCLK period. For example,

if the SYSCLK frequency is 1 GHz (1000 ps period), then a

reasonable sync validation delay value is 4 (~300 ps). This

allows the validation block to ensure that the local SYSCLK

and the delayed SYNC_IN edges exhibit at least 300 ps of

timing separation. Choosing too large a value can cause the

validation block to indicate a setup/hold violation when one

does not exist. Choosing too small a value can cause the

validation block to miss a setup/hold violation when one

actually exists.

SYNC

PULSE

SYSCLK

DELAY

SYNC VALIDATION

DELAY

SYNC_SMP_ERR

SYNC RECEIVER

SYNC TIMING VALIDATION DISABLE

SETUP

VALIDATION

HOLD

VALIDATION

SETUP AND HOLD VALIDATION

CLOCK

GENERATION

LOGIC

FROM

SYNC

RECEIVER

DELAY

LOGIC

DELAY

RISING EDGE

DETECTOR

AND STROBE

GENERATOR

Figure 58. Sync Timing Validation Block

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