TMSC6701 datasheet(34/64 Pages) TI

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TMS320C6701

FLOATINGPOINT DIGITAL SIGNAL PROCESSOR

SPRS067E – MAY 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SYNCHRONOUS-BURST MEMORY TIMING

timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK)

(see Figure 14)

NO.

’C6701-120

’C6701-150

’C6701-167

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(EDV-SSCLKH)

Setup time, read EDx valid before SSCLK high

2.0

th(SSCLKH-EDV)

Hold time, read EDx valid after SSCLK high

2.9

2.1

switching characteristics for synchronous-burst SRAM cycles† (full-rate SSCLK)

(see Figure 14 and Figure 15)

NO.

PARAMETER

’C6701-120

’C6701-150

’C6701-167

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

tosu(CEV-SSCLKH)

Output setup time, CEx valid before SSCLK high

0.5P – 1.3

toh(SSCLKH-CEV)

Output hold time, CEx valid after SSCLK high

0.5P – 2.9

0.5P – 2.3

tosu(BEV-SSCLKH)

Output setup time, BEx valid before SSCLK high

0.5P – 1.3

0.5P – 1.6

toh(SSCLKH-BEIV)

Output hold time, BEx invalid after SSCLK high

0.5P – 2.9

0.5P – 2.3

tosu(EAV-SSCLKH)

Output setup time, EAx valid before SSCLK high

0.5P – 1.3

0.5P – 1.7

toh(SSCLKH-EAIV)

Output hold time, EAx invalid after SSCLK high

0.5P – 2.9

0.5P – 2.3

tosu(ADSV-SSCLKH)

Output setup time, SSADS valid before SSCLK high

0.5P – 1.3

toh(SSCLKH-ADSV)

Output hold time, SSADS valid after SSCLK high

0.5P – 2.9

0.5P – 2.3

tosu(OEV-SSCLKH)

Output setup time, SSOE valid before SSCLK high

0.5P – 1.3

toh(SSCLKH-OEV)

Output hold time, SSOE valid after SSCLK high

0.5P – 2.9

0.5P – 2.3

tosu(EDV-SSCLKH)

Output setup time, EDx valid before SSCLK high

0.5P – 1.3

toh(SSCLKH-EDIV)

Output hold time, EDx invalid after SSCLK high

0.5P – 2.9

0.5P – 2.3

tosu(WEV-SSCLKH)

Output setup time, SSWE valid before SSCLK high

0.5P – 1.3

toh(SSCLKH-WEV)

Output hold time, SSWE valid after SSCLK high

0.5P – 2.9

0.5P – 2.3

† When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN

low) for all output hold times.

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