© 2005 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FMS6363 • Rev. 1.0.4

7

Layout Considerations

Layout and supply bypassing play major roles in high-

frequency performance and thermal characteristics.

For optimum results, follow the steps below as a basis

for high-frequency layout:

Include 10µF and 0.1μF ceramic bypass capacitors

Place the 10μF capacitor within 0.75 inches of the

power pin.

Place the 0.1μF capacitor within 0.1 inches of the

power pin.

Connect all external ground pins as tightly as

possible, preferably with a large ground plane

under the package.

Layout channel connections to reduce mutual trace

inductance.

Minimize all trace lengths to reduce series

inductances. If routing across a board, place device

such that longer traces are at the inputs rather than

the outputs. If using multiple, low-impedance DC-

coupled outputs, special layout techniques may be

employed to help dissipate heat.

If a multilayer board is used, a large ground plane

directly under the device helps reduce package case

temperature.

For dual-layer boards, an extended plane can be used.

Worst-case additional die power due to DC loading can

per channel.