AD7787

Rev. 0 | Page 13 of 20

FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0×04)

The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output

word rate. Table 11 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are

in the filter register. FR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status

of that bit.

FR7

FR6

FR5

FR4

FR3

FR2

FR1

FR0

0 (0)

0 (0)

CDIV1 (0)

CDIV0 (0)

0 (0)

FS2 (1)

FS1 (0)

FS0 (0)

Table 11. Filter Register Bit Designations

Bit

Location

Bit Name

Description

FR7 to

FR6

0

These bits must be programmed with a Logic 0 for correct operation.

FR5 to

FR4

CLKDIV1

to CDIV0

These bits are used to operate the AD7787 in the lower power modes. The clock is internally divided and the

power is reduced. In the low power modes, the update rates will scale with the clock frequency so that dividing

the clock by 2 causes the update rate to be reduced by a factor of 2 also.

00

Normal Mode

01

Clock Divided by 2

10

Clock Divided by 4

11

Clock Divided by 8

FR3

0

This bit must be programmed with a Logic 0 for correct operation.

FR2 to

FR0

FS2 to FS0

These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and the

noise. Table 12 shows the allowable update rates when normal power mode is used. In the low power modes,

the update rate is scaled with the clock frequency. For example, if the internal clock is divided by a factor of 2,

the corresponding update rates are divided by 2 also.

Table 12. Update Rates

FS2

FS1

FS0

f3dB (Hz)

RMS Noise (µV)

Rejection

0

0

0

120

28

40

25 dB @ 60 Hz

0

0

1

100

24

25

25 dB @ 50 Hz

0

1

0

33.3

8

3.36

0

1

1

20

4.7

1.6

80 dB @ 60 Hz

1

0

0

16.6

4

1.5

65 dB @ 50 Hz/60 Hz (Default Setting)

1

0

1

16.7

4

1.5

80 dB @ 50 Hz

1

1

0

13.3

3.2

1.2

1

1

1

9.5

2.3

1.1

67 dB @ 50 Hz/60 Hz

DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0×000000)

The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from

this register, the RDY bit/pin is set.