SP3282EB datasheet(8/15 Pages) SIPEX

8 / 15 page

Date: 02/24/05

SP3282EB Intelligent +2.35V to +5.5V RS-232 Transceivers

— V

SS charge storage — During this phase of the

clock cycle, the positive side of capacitors C

1 and

2 are initially charged to VCC. Cl

+ isthenswitched

to GND and the charge in C

– is transferred to C

–

. Since C

+ is connected to V

CC, the voltage poten-

tial across capacitor C

2 is now 2 times VCC.

Phase 2 (Figure 12)

— V

SS transfer — Phase two of the clock

connects the negative terminal of C

2 to the VSS

storage capacitor and the positive terminal of C

2 to

GND. This transfers a negative generated voltage

This

generated

voltage

regulated to a minimum voltage of -5.5V (V

CC >

3.3V) and -4.0V (V

CC < 3.1V).

Simultaneous with the transfer of the voltage to C

the positive side of capacitor C

1 is switched to VCC

and the negative side is connected to GND.

Phase 3 (Figure 13)

— V

DD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C

1 produces –VCC in the negative

terminal of C

1, which is applied to the negative side

of capacitor C

2. Since C2

+ is at V

CC, the voltage

potential across C

2 is 2 times VCC.

Phase 4 (Figure 14)

— V

DD transfer — The fourth phase of the clock

connects the negative terminal of C

2 to GND, and

transfers this positive generated voltage across C

to C

4, the VDD storage capacitor. This voltage is

regulated to +5.5V (V

CC > 3.3V) and +4.0V

CC<3.1V). At this voltage, the internal oscillator

is disabled. Simultaneous with the transfer of the

voltage to C

4, the positive side of capacitor C1 is

switched to V

CC and the negative side is connected

to GND, allowing the charge pump cycle to begin

again. The charge pump cycle will continue as

long as the operational conditions for theinternal

oscillator are present.

Since both V+ and V– are separately generated

Charge Pump Capacitor Selection

The charge pump capacitors C1-C4 and bypass

C5 can be of any type including ceramic. If

polarized capacitors are used, refer to figure 3

application diagram for proper orientation. The

following chart illustrates the minimum capaci-

tor valve for a given input voltage range.

from V

CC, in a no–load condition V

+ and V– will be

symmetrical. Older charge pump approaches that

generate V– from V+ will show a decrease in the

magnitude of V– compared to V+ due to the

inherent inefficiencies in the design.

The clock rate for the charge pump typically

operatesat500kHz. Theexternalcapacitors should

be 0.22

µF with a 16V working voltage rating for

a V

CC input range of +2.35V to +5.5V.

Figure 11. Charge Pump — Phase 1

VCC

VDD Storage Capacitor

VSS Storage Capacitor

-VCC

+VCC

CC (V)

C1 and C5 (

µF)

C2,C3,C4 (

µF)

3.0 to 3.6

0.1

4.5 to 5.5

0.047

0.33

2.35 to 5.5

0.22

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