AR0230CSSC00SUEAH3-GEVB datasheet(3/24 Pages) ONSEMI

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AR0230CS

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Figure 1. Block Diagram of AR0230CS

ADC Data

Row Noise Correction

Black Level Correction

Test Pattern Generator

Pixel Defect Correction

Adaptive CD Filter

Digital Gain and Pedestal

A−Law Compression

HISPI

Parallel

ADC Data

Row Noise Correction

Black Level Correction

Test Pattern Generator

Pixel Defect Correction

Adaptive CD Filter

Row Noise Correction

Digital Gain and Pedestal

Motion Correction

HDR Linearization

Smoothing Filter

Companding or ALTM

HISPI

Parallel

16 bits

14 or 12 bits

12 bits

10 bits

User interaction with the sensor is through the two−wire

serial bus, which communicates with the array control,

analog signal chain, and digital signal chain. The core of the

sensor is a 2.1 Mp Active− Pixel Sensor array. The timing

and control circuitry sequences through the rows of the

array, resetting and then reading each row in turn. In the time

interval between resetting a row and reading that row, the

pixels in the row integrate incident light. The exposure is

controlled by varying the time interval between reset and

readout. Once a row has been read, the data from the

columns is sequenced through an analog signal chain

(providing offset correction and gain), and then through an

analog−to−digital converter (ADC). The output from the

ADC is a 12−bit value for each pixel in the array. The ADC

output passes through a digital processing signal chain

(which provides further data path corrections and applies

digital gain). The sensor also offers a high dynamic range

mode of operation where multiple images are combined

on−chip to produce a single image at 16−bit per pixel value.

A compression mode is further offered to allow the 16 bits

per pixel to be transmitted to the host system as a 12−bit

value with close to zero loss in image quality.

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