TLF5107

January 1988

MM54HC153MM74HC153

Dual 4-Input Multiplexer

General Description

This 4-to-1 line multiplexer utilizes advanced silicon-gate

CMOS technology It has the low power consumption and

high noise immunity of standard CMOS integrated circuits

This device is fully buffered allowing it to drive 10 LS-TTL

loads Information on the data inputs of each multiplexer is

selected by the address on the A and B inputs and is pre-

sented on the Y outputs Each multiplexer possesses a

strobe input which enables it when taken to a low logic lev-

el When a high logic level is applied to a strobe input the

output of its associated multiplexer is taken low

The 54HC74HC logic family is functionally and pinout com-

patible with the standard 54LS74LS logic family All inputs

are protected from damage due to static discharge by inter-

Features

Y

Typical propagation delay 24 ns

Y

Wide power supply range 2V – 6V

Y

Low quiescent current 80 mA maximum (74HC Series)

Y

Low input current 1 mA maximum

Y

Fanout of 10 LS-TTL loads

Connection Diagram

Dual-In-Line Package

TLF5107 – 1

Top View

Order Number MM54HC153 or MM74HC153

Truth Table

Select

Data Inputs

Strobe

Output

Inputs

B

A

C0

C1

C2

C3

G

Y

X

X

XXXX

H

L

L

L

L

XXX

L

L

L

L

H

XXX

L

H

L

H

XLX

X

L

L

L

H

XHX

X

L

H

H

L

X

XLX

L

L

H

L

X

XHX

L

H

H

H

XXX

L

L

L

H

H

XXX

H

L

H

Select inputs A and B are common to both sections

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A