FPD87352CXA datasheet(3/5 Pages) NSC

3 / 5 page

Block Diagram

Function Description

FPD-LINK RECEIVER

The LVDS based FPD-Link Receiver receives input video

data and control timing. Four LVDS channels plus clock

provide 24-bit color.

RESETN initializes the chip with the default register values

for the LUT values from internal ROM or external EEPROM.

SSC (SPREAD SPECTRUM CONTROL)

This SSC function provides a means for reducing EMI. This

feature uses external SSC signal source that provides syn-

chronized spread spectrum for RSDS and control signal

outputs.

2-WIRE SERIAL EEPROM INTERFACE

The Serial EEPROM Interface controls the FPD87352CXA

initialization of LUT register. If the EEPROM is not present,

the

LUT

value

provided

internal

ROM

FPD87352CXA.

CLK & DATA SYNCHRONIZER

This function delays and aligns data to match the internal

data process which included RSDS skew control by

RSKEW[2:0]. All the data processes are needed to be

aligned each data path through RSDS output and LCD tim-

ing control signal.

LUT REGISTER

This block provides the RTC reference values to be pro-

cessed on the RTC Data Processor Block. The setting of

RTC reference values is provided by the external EEPROM

in normal condition. If the external EEPROM is not present it

will use the internal ROM’s RTC reference values. The RTC

reference values are the new gray values depending on the

difference between the current frames’ RGB gray data and

the previous frame’s RGB gray data of same pixel.

RTC DATA PROCESSOR

This function generates new gray values depending on the

difference of the current RGB gray data and same pixel of

the previous frame. The reference values fetch from the LUT

(Look Up Table) values in the LUT Register.

RSDS INTERFACE WITH SKEW CONTROL

This functional block transforms CMOS level signal to RSDS

for the system clock (DCLK) and RGB color data. The RSDS

skew is controlled by RSKEW[2:0] with delay steps between

the RSF/BCKP/N and RSF/BR/G/B[3:0]P/N which is imple-

mented in CLK & Data synchronizer.

20116202

FIGURE 2. Block Diagram

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