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HM628128ALP-7SL 데이터시트(PDF) 13 Page - Hitachi Semiconductor |
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HM628128ALP-7SL 데이터시트(HTML) 13 Page - Hitachi Semiconductor |
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13 / 13 page ![]() Notes: 1. 20 µA max at Ta = 0 to 40˚C (L-version). 2. 6 µA max at Ta = 0 to 40˚C (L-L-version). 3. 3 µA max at Ta = 0 to 40˚C (L-SL-version). 4. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. 13 HM628128A Series |
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