| 전자부품 데이터시트 검색엔진 |
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KESTX01MPAS 데이터시트(PDF) 4 Page - Zarlink Semiconductor Inc |
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KESTX01MPAS 데이터시트(HTML) 4 Page - Zarlink Semiconductor Inc |
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4 / 10 page ![]() 3 KESTX01 ELECTRICAL CHARACTERISTICS A.C. T amb = –40 °C to + 85°C, V CC = 3.5V to 6.5V. These characteristics are guaranteed by either production test, characterisation or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Parameter Symbol Value Units Conditions Min Typ Max Output current at IF75 1.4 2.1 2.8 pk–pk I mod =75 µA, F o =434MHz fundamental, V CC=3.5V mA Output current at IF150 2.4 3.8 4.9 pk-pk I mod =150 µA, F o =434MHz Fundamental, V CC = 3.5V mA Output current IF150(6V5) 3.0 4.6 5.6 pk–pk I mod =150µA, F o =434MHz fundamental V CC = 6.5V mA Output level at 2 x –32 dBc I mod =150µA, F o =434MHz fundamental see note 1 (1) Output level at 3 x –11 dBc I mod =150µA, F o =434MHz (1) fundamental and all other spurii see note 1 Phase detector gain PDG 4.7 8 9.5 µA/rad V CC = 3.5V Extinction ratio ER 40 dB see note 2 VCO gain G VCO 110 MHz/V TXEN settling time Txe 5.0 ms see note 3 Output sidebands due to SB –40 dBc I mod =150µA, F o =434MHz reference frequency see note 4 (1, 4) 30dB rise timeRF envelope T30R 380 ns of Data pulse 30dB fall timeRF envelope T30F 430 ns of Data pulse VCO operating frequency 400 434 460 MHz V CC = 3.5 Notes: 1. The spurii are specified relative to the fundamental, measured in a 300KHz resolution bandwidth. 2. Extinction ratio is defined as the ratio of the output power SPACE to output power MARK measured at the output operating fequency. 3. Regulatory issues demand that transmission does not take place until the PLL has acquired lock and the VCO is operating at its final output frequency. This requirement demands that pin TXEN is set high at least Txe ms prior to the transmission of any data. This value is dependent on the PLL loop bandwidth and hence on the value of the external loop filter component values. The specification value above is for the loop filter components shown in the applications diagram (Figure. 6) 4. Sidebands on the output due to the PLL reference are a function of the PLL loop bandwidth and the application. Reducing the closed loop bandwidth of the PLL loop will aid in reducing the level of the PLL reference spurii. |
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