LP3962 datasheet(14/22 Pages) NSC

14 / 22 page

Applications Information (Continued)

has a built in hysteresis. The timing diagram in

Figure 1

shows the relationship between the ERROR and the output

voltage. In this example, the input voltage is changed to

demonstrate the functionality of the Error Flag.

The internal Error flag comparator has an open drain output

stage. Hence, the ERROR pin should be pulled high through

a pull up resistor. Although the ERROR pin can sink current

of 1mA, this current is energy drain from the input supply.

Hence, the value of the pull up resistor should be in the

range of 10k

Ω to 1MΩ. The ERROR pin must be con-

nected to ground if this function is not used. It should

also be noted that when the shutdown pin is pulled low, the

ERROR pin is forced to be invalid for reasons of saving

power in shutdown mode.

Sense Pin

In applications where the regulator output is not very close to

the load, LP3965 can provide better remote load regulation

using the SENSE pin.

Figure 2 depicts the advantage of the

SENSE option. LP3962 regulates the voltage at the output

pin. Hence, the voltage at the remote load will be the regu-

lator output voltage minus the drop across the trace resis-

tance. For example, in the case of a 3.3V output, if the trace

resistance is 100m

Ω, the voltage at the remote load will be

3.15V with 1.5 A of load current, I

LOAD. The LP3965 regu-

lates the voltage at the sense pin. Connecting the sense pin

to the remote load will provide regulation at the remote load,

as shown in

Figure 2. If the sense option pin is not required,

the sense pin must be connected to the V

OUT pin.

10126607

FIGURE 1. Error Flag Operation

LP3962 데이터시트(PDF) 14 Page - National Semiconductor (TI)