ACE24CP02C

I

2

C-Compatible Serial EEPROM

VER 1.1

9

(C)

Acknowledge Polling

Once the internally timed write cycle has started and the ACE24CP02C inputs are disabled,

acknowledge polling can be initiated. This involves sending a start condition followed by the device

address word. The read/write bit is representative of the operation desired. Only if the internal write

cycle has completed will the ACE24CP02C respond with a “0”, allowing the read or write sequence

to continue.

Read Operations

Read operations are initiated the same way as write operations with the exception that the read/write

select bit in the device address word is set to “1”. There are three read operations: Current Address Read;

Random Address Read and Sequential Read.

(A)

Current Address Read

The internal data word address counter maintains the last address accessed during the last read or

write operation, incremented by one. This address stays valid between operations as long as the

chip power is maintained. The address roll-over during read is from the last byte of the last memory

page to the first byte of the first page.

Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by

the ACE24CP02C, the current address data word is serially clocked out. The microcontroller does

not respond with an input “0” but does generate a following stop condition (see Figure 9).

Figure9：Current Address Read