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ST72F324J 데이터시트(PDF) 100 Page - STMicroelectronics

부품명 ST72F324J
상세설명  8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
PDF  156 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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ST72F324J 데이터시트(HTML) 100 Page - STMicroelectronics

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
Read/Write
Reset Value: 0000 0000 (00 h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Bits 7:0 = ERPR[7:0]
8-bit Extended Receive
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 56) is divided by
the binary factor set in the SCIERPR register (in
the range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Reset Value:0000 0000 (00h)
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
Bits 7:0 = ETPR[7:0]
8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 56) is divided by
the binary factor set in the SCIETPR register (in
the range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
70
ERPR
7
ERPR
6
ERPR
5
ERPR
4
ERPR
3
ERPR
2
ERPR
1
ERPR
0
70
ETPR
7
ETPR
6
ETPR
5
ETPR
4
ETPR
3
ETPR
2
ETPR
1
ETPR
0



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