ST72F324J datasheet(127/156 Pages) STMICROELECTRONICS

127 / 156 page

ST72324J/K

127/156

CLOCK CHARACTERISTICS (Cont’d)

12.5.5 Clock Security System (CSS)

Note:

1. Data based on characterization results.

12.5.6 PLL Characteristics

Operating conditions: VDD 3.8 to 5.5V @ TA 0 to 70°C

1) or V

DD 4.5 to 5.5V @ TA -40 to 125°C

Note:

1. Data characterized but not tested.

Figure 72. PLL Jitter vs. Signal frequency1

The user must take the PLL jitter into account in

the application (for example in serial communica-

tion or sampling of high frequency signals). The

PLL jitter is a periodic effect, which is integrated

over several CPU cycles. Therefore the longer the

period of the application signal, the less it will be

impacted by the PLL jitter.

Figure 72 shows the PLL jitter integrated on appli-

cation signals in the range 125kHz to 2MHz. At fre-

quencies of less than 125KHz, the jitter is negligi-

ble.

Note 1: Measurement conditions: fCPU = 4MHz, TA= 25°C

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSFOSC

Safe Oscillator Frequency 1)

3MHz

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDD(PLL)

PLL Operating Range

TA 0 to 70°C

3.8

5.5

TA -40 to +125°C

4.5

5.5

fOSC

PLL input frequency range

MHz

fCPU/∆ fCPU

Instantaneous PLL jitter 1)

fOSC = 4 MHz.

1.0

2.5

fOSC = 2 MHz.

2.5

4.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

2000

1000

500

250

125

Application Signal Frequency (KHz)

PLL ON

PLL OFF

ST72F324J 데이터시트(PDF) 127 Page - STMicroelectronics

ST72F324J 데이터시트(HTML) 127 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL