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ST72F324J 데이터시트(PDF) 143 Page - STMicroelectronics

부품명 ST72F324J
상세설명  8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
PDF  156 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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ST72F324J 데이터시트(HTML) 143 Page - STMicroelectronics

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10-BIT ADC CHARACTERISTICS (Cont’d)
12.12.1 ADC Accuracy
Conditions: VDD=5V
Notes:
1. Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being
performed on any analog input.
Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative
current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC
accuracy.
2. Data based on characterization results, monitored in production.
Figure 97. ADC Accuracy Characteristics
Symbol
Parameter
Conditions
Typ
Max
Unit
|ET|
Total unadjusted error1)
4
LSB
EO
Offset error 1)
3
3.52)
EG
Gain Error 1)
-0.5
-22)
|ED|
Differential linearity error 1)
CPU in run mode @ fADC 2 MHz.
1.5
4.52)
|EL|
Integral linearity error 1)
CPU in run mode @ fADC 2 MHz.
1.5
4.52)
EO
EG
1LSBIDEAL
1LSB
IDEAL
V
AREF
V
SS A
1024
--------------------------------------------
=
Vin (LSBIDEAL)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
Digital Result ADCDR
1023
1022
1021
5
4
3
2
1
0
7
6
1234
567
1021 1022 1023 1024
(1)
(2)
ET
ED
EL
(3)
VAREF
VSSA



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