1 Features
• AC types feature 1.5V to 5.5V operation and
balanced noise immunity at 30% of the supply
voltage
• Speed of bipolar F, AS, and S, with significantly
reduced power consumption
• Balanced propagation delays
• ±24mA output drive current
– Fanout to 15 F devices
• SCR-latchup-resistant CMOS process and circuit
design
• Exceeds 2kV ESD protection per MIL-STD-883,
method 3015

2 Description
The CD74AC109-Q1 device contains two
independent J-K positive edge triggered flip-flops. A
low level at the preset (PRE) or clear (CLR) inputs
sets or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs that meets the
setup-time requirements is transferred to the outputs
on the positive-going edge of the clock (CLK) pulse.
The device is qualified for automotive applications.