3 Pin Configuration and Functions

Figure 3-1. CD54AC109 J Package; CD74AC109 D or N Package; 16-Pin CDIP, SOIC or PDIP (Top View)

Table 3-1. Pin Functions

PIN

I/O(1)

DESCRIPTION

NAME

NO.

1CLR

1

I

Active low clear for first channel

1J

2

I

J input for first channel

1K

3

I

Active low K input for first channel

1CLK

4

I

CLK input for first channel

1PRE

5

I

Active low Preset input for first channel

1Q

6

O

True Q output for first channel

1Q

7

O

Inverted Q output for first channel

GND

8

-

Ground

2Q

9

O

True Q output for second channel

2Q

10

O

Inverted Q output for second channel

2PRE

11

I

Active low preset for second channel

2CLK

12

I

Clock input for second channel

2K

13

I

Active low K input for second channel

2J

14

I

J input for second channel

2CLR

15

I

Active low clear for second channel

VCC

16

-

Power pin

(1)

I = input, O = output, P = power, FB = feedback, GND = ground, N/A = not applicable

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CD54AC109, CD74AC109

SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024

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