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AD5522JSVDZ 데이터시트(PDF) 14 Page - Analog Devices |
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AD5522JSVDZ 데이터시트(HTML) 14 Page - Analog Devices |
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14 / 65 page ![]() Data Sheet AD5522 Rev. E | Page 13 of 64 Circuit and Timing Diagrams TO OUTPUT PIN DVCC RLOAD 2.2kΩ CLOAD 50pF VOL Figure 3. Load Circuit for CGALM, TMPALM VOH(MIN) – VOL(MAX) 2 200µA IOL 200µA IOH TO OUTPUT PIN CLOAD 50pF Figure 4. Load Circuit for SDO, BUSY Timing Diagram SYNC SCLK SDI BUSY RESET 1 1 2 t3 t2 29 t4 t6 t5 t1 t7 t8 t9 DB28 (N) DB0 (N) DB28 (N+1) DB0 (N + 1) 29 t10 t16 t17 BUSY 1LOAD ACTIVE DURING BUSY. 2LOAD ACTIVE AFTER BUSY. LOAD1 FOHx1 LOAD2 FOHx2 t11 t12 t13 t14 t12 t15 Figure 5. SPI Write Timing (Write Word Contains 29 Bits) |
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