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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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BLUENRG-2 데이터시트(PDF) 46 Page - STMicroelectronics |
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BLUENRG-2 데이터시트(HTML) 46 Page - STMicroelectronics |
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46 / 190 page  Functional details BlueNRG-2 46/190 DocID030675 Rev 2 Figure 11: DMA request mapping in BlueNRG-2 3.7.3 DMA registers DMA peripheral base address (DMA_BASE_ADDR) 0xA0000000. Table 43: DMA registers Address offset Name RW Reset Description 0x00 ISR R 0x00000000 DMA interrupt status register. Refer to the detailed description below. 0x04 IFCR W 0x00000000 DMA interrupt flag clear register. Refer to the detailed description below. Table 44: DMA - ISR register description: address offset DMA_BASE_ADDR+0x00 Bit Field name Reset RW Description 0 GIF0 0x0 R Channel 0 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register. 0: No TE, HT or TC event on channel 0. 1: A TE, HT or TC event occurred on channel 0. |
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