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LTC5100 데이터시트(PDF) 48 Page - Linear Technology

부품명 LTC5100
상세설명  3.3V, 3.2Gbps VCSEL Driver
PDF  52 Pages
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제조업체  LINER [Linear Technology]
홈페이지  http://www.linear.com
Logo LINER - Linear Technology

LTC5100 데이터시트(HTML) 48 Page - Linear Technology

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LTC5100
48
sn5100 5100fs
APPLICATIO S I FOR ATIO
The termination resistor, R1, and its decoupling capacitor,
C1, are placed as close as possible to the LTC5100 to
reduce inductance. Inductance in these two components
causes high frequency peaking and overshoot in the
current delivered to the laser. R1 and C1 are folded against
each other so that their mutual inductance and counter-
flowing current partially cancel their self-inductance. C1
has two vias to the ground plane and a trace directly to Pin
12. The layout shows the EEPROM placed next to the
LTC5100. However, placement of the EEPROM is not
critical. It can be placed several centimeters from the
LTC5100 or on the back of the PC board if desired.
The transmission line connecting the MODB pin to the
laser has a short length of minimum width trace. The net
inductance of this section of trace helps compensate on-
chip capacitance to further reduce reflections from the
chip.
FAULT
SDA
SCL VDD(HS)
VDD
VSS
IN+
IN–
VSS
VSS
MODA
MODB
VSS
EN
SRC
LTC5100
MD
13
12
R1
50
Ω
C1
10nF
ZO = 50Ω
11
10
9
1
L1
FERRITE
BEAD
ENABLE
+TX_DATA
–TX_DATA
FAULT
VDD + 3.3V
VSS
2
3
4
14
15
16
8
FIBER
C3
10nF
24LC00
EEPROM
SOT23 PACKAGE
PROGRAMMING
PADS
5100 F29
7
6
5
ZO = 50Ω
C2
10nF
VCC
NC
SCL
VSS
SDA
C3
IN+
VSS
IN–
EEPROM
C1
R1
L1
2
3
VSS
VSS
5100 F32
MODA
MODB
1
16
15
14
13
VSS 4
11
10
12
9
5678
C2
SCL
VCC
VSS
SDA
NC
Figure 31. Schematic of a Minimum Output Reflection Coefficient Circuit
Figure 32. Layout of the Minimum Reflection Coeffieicnt Circuit Using 0402 Passive Components



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