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STA1078 데이터시트(PDF) 6 Page - STMicroelectronics |
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STA1078 데이터시트(HTML) 6 Page - STMicroelectronics |
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6 / 16 page ![]() System description STA1074, STA1078, STA1079, STA1088 6/16 DocID028356 Rev 1 2.5.1 Routing and sample rate converters Each audio interface can be routed in both directions (IN/OUT) through sample rate converters, which allow normalizing the sampling rate to the sound processing engine. The audio routing infrastructure is designed to deliver high quality sample rate conversion on multiple channels, allowing simultaneous audio streams, such as Bluetooth Hands Free, to be handled without CPU load. In order to generate multiple sampling rate audio frequencies, a dedicated fractional PLL is also provided. This PLL also allows an efficient implementation of cellular modem playback, by dynamically adjusting the reconstructed audio sampling rate without CPU overload. 2.5.2 DSP Subsystem Some devices in Telemaco2 family are equipped with an embedded DSP subsystem dedicated to sound processing and other signal processing intensive tasks, like echo/noise cancellation, sound effects generation. DSP subsystem is integrated with the sound subsystem with a specific isochronous bus. Each DSP is connected to other DSPs and audio peripherals by means of an isochronous bus infrastructure which guarantees a controlled throughput and latency for all audio transfers. 2.6 Secure CAN subsystem Telemaco2 family devices allow isolating critical code from main application by implementing a dedicated subsystem based on ARM Cortex-M3, along with: Dedicated embedded SRAM CAN controller Dedicated GPIOs In order to guarantee security of CAN network, all of the above can be completely isolated from the rest of the system, in such a way that no application running on CorteX-R4 can access by any mean to CAN specific re-sources. This subsystem can also be dedicated to implement secure features, such as boot authentication, as well as interrupt intensive tasks to offload main CPU. The secure subsystem communicates with the application running on CortexR4 using a Hardware Mailbox interrupt based mechanism. |
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