FDMF6705 datasheet(16/21 Pages) ONSEMI

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FDMF6705 • Rev. 1.0.4

Application Information

Supply Capacitor Selection

For the supply inputs (VDRV & VCIN), a local ceramic

bypass capacitor is required to reduce noise and to

supply peak transient currents during gate drive

switching action. It is recommended to use a minimum

capacitor value of 1 µF X7R or X5R. Keep this capacitor

close to the VCIN and VDRV pins and connect it to the

GND plane with vias.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor

(CBOOT), as shown in Figure 28. A bootstrap capacitance

of 100 nF X7R or X5R capacitor is typically adequate. A

series bootstrap resistor would be needed for specific

applications to improve switching noise immunity. The

boot resistor (RBOOT) may be required when operating

near the maximum rated VIN and is effective at controlling

the high-side MOSFET turn-on slew rate and VSHW

overshoot. Typical RBOOT values from 0.5 Ω to 3.0 Ω are

effective in reducing VSWH overshoot for the FDMF6705.

VCIN Filter

The VDRV pin provides power to the gate drive of the

high-side and low-side power MOSFETs. In most cases,

VDRV can be connected directly to VCIN, which

supplies power to the logic circuitry of the gate driver.

For additional noise immunity, an RC filter can be

inserted between VDRV and VCIN. Recommended

values of 10 Ω (RVCIN) placed between VDRV and VCIN

and 1 µF (CVCIN) from VCIN to CGND (see Figure 29).

Power Loss and Efficiency

Measurement and Calculation

Refer to Figure 28 for power loss testing method.

Power loss calculations are:

PIN=(VIN x IIN) + (V5V x I5V) (W)

(1)

PSW=VSW x IOUT (W)

(2)

POUT=VOUT x IOUT (W)

(3)

PLOSS_MODULE=PIN - PSW (W)

(4)

PLOSS_BOARD=PIN - POUT (W)

(5)

EFFMODULE=100 x PSW/PIN (%)

(6)

EFFBOARD=100 x POUT/PIN (%)

(7)

Figure 28. Power Loss Measurement Block Diagram

Figure 29. Block Diagram with VCIN Filter

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