VDP3108B datasheet(39/72 Pages) MICRONAS

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PRELIMINARY DATA SHEET

VDP 31xxB

Micronas

Table 3–3: Control Registers of the Fast Processor for control of front-end functions

– default values are initialized at reset

FP Sub-

address

Function

Default

Name

Standard Selection

h’20

Standard select:

bit[2:0]

standard

PAL B,G,H,I (50 Hz)

4.433618

NTSC M

(60 Hz)

3.579545

SECAM

(50 Hz)

4.286

NTSC44

(60 Hz)

4.433618

PAL M

(60 Hz)

3.575611

PAL N

(50 Hz)

3.582056

PAL 60

(60 Hz)

4.433618

NTSC COMB (60 Hz)

3.579545

bit[3]

0/1

standard modifier

PAL modified to simple PAL

NTSC modified to compensated NTSC

SECAM modified to monochrome 625

NTSCC modified to monochrome 525

bit[4]

reserved (set to 0)

bit[5]

0/1

2-H comb filter off/on

bit[6]

0/1

S-VHS mode off/on

Option bits allow to suppress parts of the initialization, this can be used

for color standard search:

bit[7]

no hpll setup

bit[8]

no vertical setup

bit[9]

no acc setup

bit[10]

2-H comb filter set-up only

bit[11]

status bit, normally write 0. After the FP has switched to a

new standard, this bit is set to 1 to indicate operation

complete. Standard is automatically initialized when the

insel register is written.

sdt

pal

ntsc

secam

ntsc44

palm

paln

pal60

ntscc

sdtmod

comb

svhs

sdtopt

h’22

picture start position, this register sets the start point of active video, this

can be used e.g. for panning. The setting is updated when ’sdt’ register

is updated.

sfif

h’23

luma/chroma delay adjust. The setting is updated when ’sdt’ register is

updated.

bit[5:0]

reserved, set to zero

bit[11:6]

luma delay in clocks, allowed range is +1 ... –7

ldly

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