PSD813F2 datasheet(95/110 Pages) STMICROELECTRONICS

95 / 110 page

95/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 62. Port A Peripheral Data Mode READ Timing (3V devices)

Figure 48. Peripheral I/O WRITE Timing

Table 63. Port A Peripheral Data Mode WRITE Timing (5V devices)

Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).

2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.

3. Any input used to select Port A Data Peripheral mode.

4. Data is already stable on Port A.

5. Data stable on ADIO pins to data on Port A.

Symbol

Parameter

Conditions

-12

-15

-20

Turbo

Off

Unit

MinMax

tAVQV–PA

Address Valid to Data Valid

(Note 3)

+ 20

tSLQV–PA

CSI Valid to Data Valid

+ 20

tRLQV–PA

RD to Data Valid

(Notes 1,4)

RD to Data Valid 8031 Mode

tDVQV–PA

Data In to Data Out Valid

tQXRH–PA

RD Data Hold Time

tRLRH–PA

RD Pulse Width

(Note 1)

tRHQZ–PA

RD to Data High-Z

(Note 1)

Symbol

Parameter

Conditions

-70

-90

-15

Unit

Min

Max

Min

Max

Min

Max

tWLQV–PA

WR to Data Propagation Delay

(Note 2)

tDVQV–PA

Data to Port A Data Propagation Delay

(Note 5)

tWHQZ–PA

WR Invalid to Port A Tri-state

(Note 2)

tDVQV (PA)

tWLQV

(PA)

tWHQZ (PA)

ADDRESS

DATA OUT

A / D BUS

PORT A

DATA OUT

ALE /AS

AI02898

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