CS7615

DS231PP6

31

GNDA - Analog Ground, PIN 12, 15, 16, 18, 22.

Analog ground reference.

GNDD - Digital Ground, PIN 6, 40.

Digital ground reference.

Analog Input

AIN - Video Input, PIN 17.

CCD output signal.

Digital Inputs

VRST - Vertical sync reset, PIN 10.

Used to reset vertical line counter in genlock mode. VRST is falling edge triggered.

INTERP - Digital Video Horizontal Data Rate Scaler Enable, PIN 11.

Active high logic input sets CLKO output rate to 1× non-interpolated data rate, and the

CLK2XO output rate to 2× interpolated data rate (5/2× CLKO rate). Logic low causes the

CLKO output rate to be the pixel rate, while CLKX2O is set to twice the pixel rate.

FCLKIN - Frequency of crystal input, PIN 13.

Logic input identifying the external crystal as a 1× rate or a 2× rate crystal. This pin should

be set high for a 1× crystal or clock source; logic low for a 2× crystal or clock source.

RESET - Master reset, PIN 14.

May be connected to external power-on-reset-circuit. Clears registers to default values. Active

logic high.

XTALIN - Crystal input, PIN 32.

May be 1× or 2× the data rate.

XTALOUT - Oscillator output to crystal, PIN 33.

If the on-chip oscillator is used, this output connects to the crystal.

Timing Generator Outputs

HSYNC - Horizontal sync signal, PIN 7.

To be used in genlock mode. HSYNC is a rising pulse.