5812-DS01-R datasheet(67/84 Pages) BOARDCOM

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Advance Data Sheet

BCM5812

3/11/03

B roa dcom Co rpo rat ion

Document

5812-DS01-405-R

DMA Control and Status Registers

Page 59

DMA CONTROL AND STATUS REGISTERS

The DMA registers control how master command structures, command context, and packet data are fetched and stored back

after processing. All of the following registers are located in PCI memory starting at the address programmed by the host

processor into BAR0.

The various registers within the DMA control and status space are as follows.

Enables the device to generate PME. BCM5812 does not support PME pin.

7:2

RSVD

Reserved

1:0

Current power state. Can be set by writing to it.

• 00 = D0

• 01 = D1

• 02 = D2

• 03 = D3

Table 20: DMA Control and Status Register Summary

Offset

bits

16 15

bits

0x00

Master Command Record 1@

0x04

DMA Control

0x08

DMA Status

0x0C

DMA Error Address

0x10

Master Command Record 2@

Table 21: DMA Control and Status Registers

Bits

Access

Reset

Purpose

DMA Master Command Record 1@ – 0x00

31:0

Writing the address of a valid master command record to this register causes crypto/

authentication processing of the packet descriptors within that record to begin. This

initial write to this register. This allows the CPU to write a second MCR address value to

this register, effectively queuing up to MCR structures for back to back processing with

zero latency. Reset state is unknown. Do not write if PCI master mode is disabled.

DMA Control – 0x04

RESET – Software reset. Normally, it is zero. If software detects hanging or other

undesirable states of BCM5812, it writes a one to this bit to reset the BCM5812. The

BCM5812 can be used after 256 core-clock cycles.

Table 19: PCI Configuration Register Bit Fields (Cont.)

Bits

Access

Reset

Purpose

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