5812-DS01-R datasheet(69/84 Pages) BOARDCOM

69 / 84 page

Advance Data Sheet

BCM5812

3/11/03

B roa dcom Co rpo rat ion

Document

5812-DS01-405-R

DMA Control and Status Registers

Page 61

DMAERR_INTR = Interrupt status for MCR DMA master access error. Sticky until

explicitly cleared by writing a 1 to this bit position. This bit accurately reflects status even

if the corresponding interrupt enable bit is off (in which case a PCI interrupt is not

generated). Resets to 0.

MCR2_FULL flag = Master command address register is full. When this flag is 1, the CPU

must not write to the MCR2@ register. When this flag is 0, the CPU may write a value to

the MCR2@ register to request processing of a master command structure. Resets to 0.

MCR2_INTR = Completion interrupt status of per-MCR interrupt for MCR2@. Cleared by

writing a 1 to this bit position. This bit accurately reflects processing status even if the

corresponding interrupt bit is disabled (in which case a PCI interrupt is not generated).

This bit is sticky until cleared explicitly. Resets to 0.

MCR1_ALL_EMPTY = All the MCRs in the MCR1@ register are done. Cleared by writing

a 1 to this bit position or by writing a 1 to MCR1_INTR bit position. This bit is sticky until

cleared. Reset to 0.

MCR2_ALL_EMPTY = All the MCRs in the MCR2@ register are done. Cleared by writing

a 1 to this bit position or by writing a 1 to MCR2_INTR bit position. This bit is sticky until

cleared. Reset to 0.

DMA Error Address – 0x0C

31:2

Address of master access that resulted in a PCI fault (32b word address). Reset state

Unknown.

1RO

• 0 = Faulted master access was a write.

• 1 = Faulted master access was a read. Reset state Unknown.

DMA Master Command Record 2@ – 0x10

31:0

Writing the address of a valid master command record to this register causes key setup

processing of the data within that record to begin. This register must only be written when

the ‘MCR_FULL’ bit of the DMA status register is 0. This register is quadruple buffered

because BCM5812 can process two key setup MCRs simultaneously, such that the

MCR_FULL bit goes to zero very quickly after two initial writes to this register. This allows

the CPU to write third and fourth MCR address values to this register, effectively queuing

up four MCR structures for back to back processing with zero latency. Reset state is

Unknown. Do not write if PCI master mode is disabled.

Table 21: DMA Control and Status Registers (Cont.)

Bits

Access

Reset

Purpose

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