5238-DS03-405-R datasheet(39/76 Pages) BOARDCOM

39 / 76 page

Advance Data Sheet

BCM5238

1/31/03

Broa d c om Co rp o r a t i o n

Document

5238-DS03-405-R

PHY Identifier Registers

Page 31

100BASE-TX Capability. The BCM5248 is capable of 100BASE-TX half-duplex operation and returns a 1 when bit 13 of

the Status Register is read.

10BASE-T FDX Capability. The BCM5248 is capable of 10BASE-T full-duplex operation and returns a 1 when bit 12 of the

Status register is read.

10BASE-T Capability. The BCM5248 is capable of 10BASE-T half-duplex operation and returns a 1 when bit 11 of the

Status Register is read.

MF Preamble Suppression. This bit is the only writable bit in the Status register. Setting this bit to a 1 allows subsequent

MII management frames to be accepted with or without the standard preamble pattern. When preamble suppression is

enabled, only 2 preamble bits are required between successive management commands, instead of the normal 32.

Auto-Negotiation Complete. Bit 5 of the Status register returns a 1 if the auto-negotiation process has been completed and

the contents of registers 4, 5 and 6 are valid.

Auto-Negotiation Capability. The BCM5248 is capable of performing IEEE Auto-negotiation and returns a 1 when bit 4 of

the Status register is read, regardless of whether or not the auto-negotiation function has been disabled.

Link Status. The BCM5248 returns a 1 on bit 2 of the Status register when the link state machine is in Link Pass, indicating

that a valid link has been established. Otherwise, it returns 0. When a link failure occurs after the Link Pass state has been

entered, the Link Status bit is latched at 0 and remains so until the bit is read. After the bit is read, it becomes 1 if the Link

Pass state has been entered again.

Jabber Detect. 10BASE-T operation only. The BCM5248 returns a 1 on bit 1 of the Status register if a jabber condition has

been detected. After the bit is read, or if the chip is reset, it reverts to 0.

Extended Capability. The BCM5248 supports extended capability registers and returns a 1 when bit 0 of the Status register

is read. Several extended registers have been implemented in the BCM5248 and their bit functions are defined later in this

section.

PHY IDENTIFIER REGISTERS

Broadcom Corporation has been issued an Organizationally Unique Identifier (OUI) by the IEEE. It is a 24-bit number

(00-10-18) expressed as hexadecimal values. That number, along with the Broadcom model number for the BCM5238 part

(20h) and Broadcom revision number (00h) is placed into two MII registers. The translation from OUI, model number, and

revision number to the PHY Identifier register occurs as follows:

PHYID HIGH[15:0] = OUI[21:6]

PHYID LOW[15:0] = OUI[5:0] + MODEL[5:0] + REV[3:0]

Note that the two most significant bits of the OUI are not represented (OUI[23:22]).

Table 20: PHY Identifier Registers (Addresses 02d and 03d, 02h and 03h)

Bit

Name

R/W

Description

Value

15:0

MII Address 00010

PHYID HIGH

0040h

15:0

MII Address 00011

PHYID LOW

6200h

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