Kawasaki USB device

KL5KUSB201

Copyright © 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.

Figure 7-2 SIE Bus Input Timing

CKOUT (O)

TXACT (I)

TXRDY (O)

RXACT (O)

RXVLD (O)

B3

B4

B5

B6

//

//

//

//

//

B2

B1

//

8. USB Bus Timing

8.1 Bulk IN Transaction

Figure 8-1 shows the data timing of a Bulk IN transaction from USB host. When the LSI

receives IN packet from the host PC, it asserts RXACT and drives 3 bytes received

data on SIE bus. External SIE logic receives the data, checks the information of

address, endpoint and CRC if necessary. If it finds the data valid, the SIE returns the

DATA packet to be transmitted. Finally the LSI receives ACK packet and finishes a Bulk

IN transaction.

Figure 8-1 Bulk IN transaction

2'

RXACT (O)

USB Bus (IO)

SE0

IN

SE0

TXACT (I)

ep

AE

IN EC

2

DAT

3

4

n-1

n

....

....

D

3' 4'

n' C16

SE0

ep

SE0

ep

AK

....

SYNC

AEC

SYNC

SYNC AK