ADC12L080 datasheet(8/23 Pages) NSC

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AC Electrical Characteristics (Continued)

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Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

Note 9: With the test condition for VREF = +1.0V (2 VP-P differential input), the 12-bit LSB is 488 µV.

Note 10: Typical figures are at TA =TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality

Level).

Note 11: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.

Note 12: Optimum dynamic performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ or the LM4051CIM3-1.2

band gap voltage reference is recommended for this application.

Note 13: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,

VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 xf0 +C1 xf1 +....C11 xf11) where VDR is the output driver power supply

voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling.

Note 14: Power consumption excludes output driver power. See (Note 13).

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