Data Sheet

AD8366

Rev. B | Page 7 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED

TO GROUND.

VPSIA

IPPA

IPMA

ENBL

ICOM

IPMB

IPPB

VPSIB

BIT0/CS

BIT1/SDAT

BIT2/SCLK

BIT3

OCOM

BIT4

BIT5

DENA

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

AD8366

TOP VIEW

(Not to Scale)

Figure 4. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 8, 13, 28

VPSIA, VPSIB, VPSOB,

VPSOA

Input and Output Stage Positive Supply Voltage (4.75 V to 5.25 V).

2, 3, 6, 7

IPPA, IPMA, IPMB,

IPPB

Differential Inputs.

4

ENBL

Chip Enable. Pull this pin high to enable.

5, 20

ICOM, OCOM

Input and Output Ground Pins. Connect these pins via the lowest possible impedance to

ground.

9, 32

DECB, DECA

ground.

10, 31

OFSB, OFSA

Output Offset Correction Loop Compensation. Connect a capacitor from these nodes to

ground to enable the correction loop. Tie this pin to ground to disable.

11, 30

CCMB, CCMA

Connect These Nodes to Ground.

12, 29

VCMB, VCMA

from a low impedance source to change the output common-mode voltage.

14, 15, 26, 27

OPPB, OPMB, OPMA,

OPPA

Differential Outputs.

16, 17

DENB, DENA

Data Enable. Pull these pins high to address each or both channels for parallel gain

programming. These pins are not used in serial mode.

18, 19, 21, 22, 23, 24

BIT5, BIT4, BIT3,

BIT2/SCLK, BIT1/SDAT,

BIT0/CS

Parallel Data Path (When SENB Is Low). When SENB is high, BIT0 becomes a chip select (CS),

BIT1 becomes a serial data input (SDAT), and BIT2 becomes a serial clock (SCLK). BIT3 to BIT5

are not used in serial mode.

25

SENB

Serial Interface Enable. Pull this pin high for serial gain programming mode and pull this pin low

for parallel gain programming mode.

EPAD

The exposed pad must be connected to ground.