| 전자부품 데이터시트 검색엔진 |
|
AD8366ACPZ-R7 데이터시트(PDF) 15 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD8366ACPZ-R7 데이터시트(HTML) 15 Page - Analog Devices |
|
15 / 28 page ![]() Data Sheet AD8366 Rev. B | Page 15 of 28 CIRCUIT DESCRIPTION The AD8366 is a dual, differential, digitally controlled VGA with 600 MHz of 3 dB bandwidth and a gain range of 4.5 dB to 20.25 dB adjustable in 0.25 dB steps. Using a proprietary variable gain architecture, the AD8366 is able to achieve excellent linearity (45 dBm) and noise performance (11.7 nV/√Hz) at 10 MHz at minimum gain. Intended for use in direct conversion systems, the part also includes dc offset correction that can be disabled easily by grounding either OFSA or OFSB. In addition, the part offers an adjustable output common-mode range of 1.6 V to 3 V. The main signal path is shown in Figure 46. It consists of an input transconductance, a variable-gain cell, and an output transimpedance amplifier. 100Ω 100Ω 12.5Ω 12.5Ω VARIABLE CURRENT-GAIN STAGE OUTPUT BUFFER Z AI VIRTUAL GROUND VIRTUAL GROUND INP INM OUTP OUTM Figure 46. Main Signal Path The input transconductance provides a broadband 200 Ω differential termination and converts the input voltage to a current. This current is fed into the variable current-gain cell. The output of this cell goes into the transimpedance stage, which generates the output voltage. The transimpedance is fixed at 500 Ω, with a roughly 25 Ω differential output impedance. INPUTS The inputs to the digitally-controlled VGAs in the AD8366 are differential and can be either ac- or dc-coupled. The AD8366 synthesizes a 200 Ω (differential) input impedance, with a return loss (re: 200 Ω) of better than 10 dB to 200 MHz. The nominal common-mode input voltage to the part is VPOS/2, but the AD8366 can be dc-coupled to parts with lower common modes if these parts can sink current. The amount of current sinking required depends on the input common-mode level and is given by ISINK (per leg) = (VPOS/2 − VICM)/100 The input common-mode range is 1.5 V to VPOS/2. OUTPUTS The outputs of the digitally-controlled VGAs are differential and can be either ac- or dc-coupled. The AD8366 synthesizes a 25 Ω differential output impedance, with a return loss (re: 25 Ω) of better than 10 dB to 120 MHz. The nominal common-mode output voltage is VPOS/2; however, it can be lowered or raised by driving the VCMA or VCMB pins. OUTPUT DIFFERENTIAL OFFSET CORRECTION To prevent significant levels of offset from appearing at the outputs of the AD8366, each digitally controlled VGA has a differential offset correction loop, as shown in Figure 47. This loop senses any differential offset at the output and corrects for it by injecting an opposing current at the input differential ground. The loop is able to correct for input dc offsets of up to ±20 mV. Because the loop automatically nulls out any dc or low frequency offset, the effect of the loop is to introduce a high-pass corner into the transfer function of the digitally controlled VGA. The location of this high-pass corner depends on both the gain setting and the value of the capacitor connected to the OFSx pin (OFSA for DVGA A and OFSB for DVGA B) and is given by ( ) ( ) ( ) 10 2π 4000 1.037 4300 kHz , 3 + + = OFS GC HP dB C f where: GC is the gain code (a value from 0 to 63). COFS is the value of the capacitance connected to OFSA or OFSB, in picofarads (pF). The offset correction loop can be disabled by grounding either OFSA or OFSB. gm1 gm2 INP INM OFFSET COMPENSATION LOOP VARIABLE-GAIN STAGE OUTPUT BUFFER Z AI OUTP OUTM COFS Figure 47. Differential Offset Correction Loop OUTPUT COMMON-MODE CONTROL To interface to ADCs that require different input common-mode voltages, the AD8366 has an adjustable output common-mode level. The output common-mode level is normally set to VPOS/2; however, it can be changed between 1.6 V and 3 V by driving the VCMA pin or the VCMB pin. The input equivalent circuit for the VCMA pin is shown in Figure 48; the VCMB pin has the same input equivalent circuit. 4kΩ 500Ω VPOS/2 VCMA Figure 48. Input Equivalent Circuit for VCMA |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |