L6911D datasheet(7/17 Pages) STMICROELECTRONICS

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L6911D

charge the output capacitor. As VSS reaches 1V (i.e. the oscillator triangular wave inferior limit) also the upper

MOS begins to switch and the output voltage starts to increase.

The VSS growing voltage initially clamps the output of the error amplifier, and consequently VOUT linearly in-

creases, as shown in figure 2. In this phase the system works in open loop. When VSS is equal to VCOMP the

clamp on the output of the error amplifier is released. In any case another clamp on the input of the error ampli-

fier remains active, allowing to VOUT to grow with a lower slope (i.e. the slope of the VSS voltage, see figure 2).

In this second phase the system works in closed loop with a growing reference. As the output voltage reaches

the desired value VPROG, also the clamp on the error amplifier input is removed, and the soft start finishes. Vss

increases until a maximum value of about 4V.

The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins

are not above their own turn-on thresholds. During normal operation, if any under-voltage is detected on one of

the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged.

The device goes in INHIBIT state forcing SS pin below 0.4V. In this condition both external MOSFETS are kept

off.

Figure 2. Soft Start

Driver Section

The driver capability on the high and low side drivers allows using different types of power MOS (also multiple

MOS to reduce the RDSON), maintaining fast switching transition.

The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.

Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mos-

fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is

avoided if the PHASE pin is over about 500mV. The upper mos is in any case turned-on after 200nS from the

low side turn-off.

The peak current is shown for both the upper (fig. 3) and the lower (fig. 4) driver at 5V and 12V. A 4nF capacitive

load has been used in these measurements.

For the lower driver, the source peak current is 1.1A @ Vcc=12V and 500mA @ Vcc=5V, and the sink peak

current is 1.3A @ Vcc=12V and 500mA @ Vcc=5V.

Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase=12V and 600mA @ Vboot-

Vphase =5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.

V cc Turn-on thre sh old

V in Turn-o n threshold

0.5 V

Vcc

Vin

Vss

LGATE

Vo ut

to G ND

Timing Diagram

Aquisition: CH1 = PHASE; CH2 = VOUT;

CH3 = PGOOD; CH4 = VSS

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