| 전자부품 데이터시트 검색엔진 |
|
LT3045 데이터시트(PDF) 22 Page - Linear Technology |
|
|
|||||||||||||||||||||||||||||
LT3045 데이터시트(HTML) 22 Page - Linear Technology |
|
22 / 36 page ![]() LT3045-1 22 30451fa For more information www.linear.com/LT3045-1 APPLICATIONS INFORMATION If OUTS is externally held above SET, the current sink turns ON in an attempt to restore OUTS to its programmed voltage. The current sink remains ON until the external circuitry releases OUTS. Direct Paralleling for Higher Current Higher output current is obtained by paralleling multiple LT3045-1s.TieallSETpinstogetherandallINpinstogether. Connect the OUT pins together using small pieces of PCB trace (used as a ballast resistor) to equalize currents in the LT3045-1s. PCB trace resistance in milliohms/inch is shown in Table 2. Table 2. PC Board Trace Resistance WEIGHT (oz) 10mil WIDTH 20mil WIDTH 1 54.3 27.1 2 27.1 13.6 Trace resistance is measured in mΩ/in. The small worst-case offset of 2mV for each paralleled LT3045-1 minimizes the required ballast resistor value. Figure 7illustratesthattwoLT3045-1s,eachusinga20mΩ PCBtraceballastresistor,providebetterthan20%accurate output current sharing at full load. The two 20mΩ external resistors only add 10mV of output regulation drop with a 1A maximum current. With a 3.3V output, this only adds 0.3% to the regulation accuracy. As has been discussed previously,tietheOUTSpindirectlytotheoutputcapacitor. More than two LT3045-1s can also be paralleled for even higher output current and lower output noise. Paralleling multiple LT3045-1s is also useful for distributing heat on thePCB.Forapplicationswithhighinput-to-outputvoltage differential, an input series resistor or resistor in parallel with the LT3045-1 can also be used to spread heat. PCB Layout Considerations Given the LT3045-1’s high bandwidth and ultrahigh PSRR, careful PCB layout must be employed to achieve full device performance. Figure 8 shows a recommended layout that delivers full performance of the regulator. Refer to the LT3045-1’s DC2593A demo board manual for further details. Figure 7. Parallel Devices Figure 8. Recommended DFN Layout 100µA IN EN/UV PGFB GND OUT LT3045-1 ILIM PG 10µF 20m VOUT 3.3V IOUT(MAX) 1A 30451 F07 16.5k SET OUTS 100µA IN EN/UV PGFB GND OUT LT3045-1 VIOC VIOC ILIM PG 10µF 20m 10µF VIN 5V ±5% SET OUTS 0.47µF |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |