MPC755 datasheet(41/56 Pages) MOTOROLA

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

System Design Information

Figure 23 describes the alternate driver impedance measurement circuit.

Figure 23. Alternate Driver Impedance Measurement Circuit

Table 18 summarizes the signal impedance results. The driver impedance values were characterized at 0°, 65°, and

105°C. The impedance increases with junction temperature and is relatively unaffected by bus voltage.

8.6 Pull-Up Resistor Requirements

The MPC755 requires pull-up resistors (1

−5kΩ) on several control pins of the bus interface to maintain the control

signals in the negated state after they have been actively negated and released by the MPC755 or other bus masters.

These pins are TS, ABB, AACK, ARTRY, DBB, DBWO, TA, TEA, and DBDIS. DRTRY should also be connected

to a pull-up resistor (1

−5kΩ) if it will be used by the system; otherwise, this signal should be connected to HRESET

to select NO-DRTRY mode (see the MPC750 RISC Microprocessor Family User’s Manual for more information on

this mode).

Three test pins also require pull-up resistors (100

Ω−1kΩ). These pins are L1_TSTCLK, L2_TSTCLK, and

LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD for normal machine

operation.

In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1

−5kΩ) if it is used by the

system.

During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may,

therefore, float in the high-impedance state for relatively long periods of time. Since the MPC755 must continually

monitor these signals for snooping, this float condition may cause additional power draw by the input receivers on

the MPC755 or by other receivers in the system. These signals can be pulled up through weak (10-k

Ω) pull-up

resistors by the system or may be otherwise driven by the system during inactive periods of the bus to avoid this

Table 18. Impedance Characteristics

VDD = 2.0 V, OVDD = 3.3 V, Tj = 0°–105°C

Impedance

Processor Bus

L2 Bus

Symbol

Unit

25–36

Ω

26–39

Ω

(L2)OVDD

BGA

Data

Vforce

OGND

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