전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

MP2624GL 데이터시트(PDF) 7 Page - Monolithic Power Systems

부품명 MP2624GL
상세설명  I2C Controlled 4.5A Single Cell USB / Adaptor Charger with Narrow VDC Power Path Management USB OTG and Shipping Mode
PDF  45 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  MPS [Monolithic Power Systems]
홈페이지  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP2624GL 데이터시트(HTML) 7 Page - Monolithic Power Systems

Back Button MP2624GL Datasheet HTML 3Page - Monolithic Power Systems MP2624GL Datasheet HTML 4Page - Monolithic Power Systems MP2624GL Datasheet HTML 5Page - Monolithic Power Systems MP2624GL Datasheet HTML 6Page - Monolithic Power Systems MP2624GL Datasheet HTML 7Page - Monolithic Power Systems MP2624GL Datasheet HTML 8Page - Monolithic Power Systems MP2624GL Datasheet HTML 9Page - Monolithic Power Systems MP2624GL Datasheet HTML 10Page - Monolithic Power Systems MP2624GL Datasheet HTML 11Page - Monolithic Power Systems Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 45 page
background image
MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG
MP2624 Rev.1.05
www.MonolithicPower.com
7
4/9/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VIN = 5V, TA = 25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max
Units
Step-Down Converter
Input voltage range
VIN
3.9
7.0
V
Input shutdown current
VIN = 5V, both DC/DC and
battery FET are disabled
65
μA
Input quiescent current
VIN > VIN_UVLO, VIN > VBATT,
charge disabled, switching,
SYS float
3
5
mA
VIN > VIN_UVLO, VIN > VBATT,
charge enabled, switching
BATT and SYS float
3
5
Input under-voltage lockout
VIN UVLO VIN rising
3.45
3.6
V
VIN_UVLO hysteresis
VIN falling
200
mV
VIN vs. VBATT headroom
VIN rising
200
250
300
mV
VIN falling
65
90
115
mV
Internal reverse-blocking
MOSFET on resistance
RIN to PMID Measure from IN to PMID
25
35
mΩ
High-side
NMOS
on
resistance
RH_DS
Measure from PMID to SW
25
35
mΩ
Low-side NMOS on resistance
RLDS
Measure from SW to PGND
28
35
mΩ
High-side NMOS peak current
limit
7.5
A
Low-side NMOS peak current
limit
7
A
Switching frequency
VBATT = 4.2V, ICHG = 2A
1.4
1.7
2.0
MHz
SYS Output
Minimum system regulation
voltage [I
2C]
VSYS_MIN
ISYS = 0, VBATT = 3.4V, POR
default, REG01[2:0] = 110
3.6
V
System regulation voltage
VSYS_MAX
50mV or 100mV (REG01[0])
higher than VBATT_FULL
depends on the I
2C setting
3.53
4.525
V
Ideal diode forward voltage in
supplement mode
VF_IDD
50mA discharge current
24
mV



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com