EM78P568

8-bit OTP Micro-controller

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* This specification are subject to be changed without notice.

34

01/31/2004

V4.7

IOCC (PORTC I/O control, ADC control)

PAGE0 (PORTC I/O control register)

7

6

5

4

3

2

1

0

IOCC7

IOCC6

IOCC5

IOCC4

IOCC3

IOCC2

IOCC1

IOCC0

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

Bit 0 ~ Bit 7 (IOCC0 ~ IOCC7) : PORTC(0~7) I/O direction control register

0

put the relative I/O pin as output

1

put the relative I/O pin into high impedance

PAGE1 (PORT switch)

7

6

5

4

3

2

1

0

PC7S

PC6S

PC5S

PBSH

PBSL

P5SH

-

-

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

Bit 0 : (remain its value to “0” unchanged otherwise Comparator and CTCSS function will fail)

Bit 1: (undefined) not allowed to use

Bit 2(P5SH) : Switch I/O PORT5 high nibble(5~7) or LCD segment signal

0

(P55 ~ P57 pins are selected) : normal PORT5 high nibble(5~7)

1

(SEG10 ~ SEG12 pins are selected) : SEGMENT output

Bit 3(PBSL) : Switch I/O PORTB low nibble(0~3) or LCD segment signal

0

(PB0 ~ PB3 pins are selected) : normal PORTB low nibble(0~3)

1

(SEG28 ~ SEG25 pins are selected) : SEGMENT output

Bit 4(PBSH) : Switch I/O PORTB high nibble(4~7) or LCD segment signal

0

(PB5 ~ PB7 pins are selected) : normal PORTB high nibble(4~7)

1

(SEG24 ~ SEG21 pins are selected) : SEGMENT output

Bit 5(PC5S) : Switch I/O PORTC5 or LCD segment signal

0

(PC5 pin is selected) : normal PORTC5

1

(SEG31 pin) : SEGMENT output

Bit 6(PC6S) : Switch I/O PORTC6 or LCD segment signal

0

(PC6 pin is selected) : normal PORTC6

1

(SEG30 pin) : SEGMENT output

Bit 7(PC7S) : Switch I/O PORTC7 or LCD segment signal

0

(PC7 pin is selected) : normal PORTC7

1

(SEG29 pin) : SEGMENT output

IOCD (TONE1 control, Clock source, Prescaler of CN1 and CN2)

PAGE0 (TONE1 control)

7

6

5

4

3

2

1

0

T17

T16

T15

T14

T13

T12

T11

T10

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

Bit 0 ~ Bit 7 (T10 ~ T17) : Tone generator 1‘s frequency divider and power control

Please Run in Normal mode.

Clock source = 111957Hz and Freq. = 111957Hz / N, where N is divider value for T1A ~ T10 (T1A ~ T18

are in the IOCE PAGE0 Bit 2 ~ Bit 0.

If T20 ~ T18 are all “0”, then

T17 ~ T10 = ‘11111111’ => Tone generator1 will has 439Hz SIN wave output.

:

T17~T10 = ‘00000010’ => Tone generator1 will has 55978Hz SIN wave output.

T17~T10 = ‘00000001’ => DC bias voltage output

T17~T10 = ‘00000000’ => Power off