EM78P568

8-bit OTP Micro-controller

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* This specification are subject to be changed without notice.

35

01/31/2004

V4.7

PAGE1 (Clock source and prescaler for COUNTER1 and COUNTER2)

7

6

5

4

3

2

1

0

CNT2S

C2_PSC2

C2_PSC1

C2_PSC0

CNT1S

C1_PSC2

C1_PSC1

C1_PSC0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

Bit 0 ~ Bit 2 (C1_PSC0 ~ C1_PSC2) : COUNTER1 prescaler ratio

C1_PSC2

C1_PSC1

C1_PSC0

COUNTER1

0

0

0

1:2

0

0

1

1:4

0

1

0

1:8

0

1

1

1:16

1

0

0

1:32

1

0

1

1:64

1

1

0

1:128

1

1

1

1:256

Bit 3(CNT1S) : COUNTER1 clock source

0/1

16.384kHz/system clock

Bit 4 ~ Bit 6 (C2_PSC0 ~ C2_PSC2) : COUNTER2 prescaler ratio

C2_PSC2

C2_PSC1

C2_PSC0

COUNTER2

0

0

0

1:2

0

0

1

1:4

0

1

0

1:8

0

1

1

1:16

1

0

0

1:32

1

0

1

1:64

1

1

0

1:128

1

1

1

1:256

Bit 7(CNT2S) : COUNTER2 clock source

0/1

16.384kHz/system clock

IOCE (Interrupt mask, TONE1 extra control bits, CTCSS control switches)

PAGE0 (Interrupt mask, TONE1 extra three control bits)

7

6

5

4

3

2

1

0

-

-

-

-

-

T1A

T19

T18

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

Bit 0 ~ Bit 2 (T18 ~ T1A) : Most significant 3 bits of Tone generator 1‘s frequency divider and power control

These 3 bits and other 8 bits (IOCA PAGE0 bit 7 ~ bit0) are assembled as 11-bit frequency divider for Tone

generator 1

Bit 3 : (undefined) not allowed to use

Bit 4 ~ Bit 7 : (remain these values to “0”othwise it will generate unpredicted interrupts)

PAGE1 (CTCSS control switches)

7

6

5

4

3

2

1

0

TXPWR

RXPWR BPFPWR

LPFPWR

ASW4

ASW3

ASW2

ASW1

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

Bit 0(ASW1) : Analog switch-1 control for multi-plexer in the CTCSS block

0

Select VRX1 input

1

Select VTX1 input