IMX6SLLCEC datasheet(39/90 Pages) NXP

39 / 90 page

Electrical Characteristics

i.MX 6SLL Applications Processors for Consumer Products, Rev. 0.2, 11/2017

NXP Semiconductors

Figure 12 shows the LPDDR2 and LPDDR3 read timing diagram. The timing parameters for this

diagram appear in Table 34.

Figure 12. LPDDR2 and LPDDR3 Read Cycle

1 To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P

in the middle of DRAM_DATA_xx window.

2 All measurements are in reference to Vref level.

3 Measurements were done using balanced load and 25

 resistor from outputs to DRAM_VREF.

4.10

External Peripheral Interface Parameters

The following subsections provide information on external peripheral interfaces.

4.10.1

AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between

internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI

electrical specifications found within this document.

4.10.2

CMOS Sensor Interface (CSI) Timing Parameters

4.10.2.1

Gated Clock Mode Timing

Figure 13 and Figure 14 shows the gated clock mode timings for CSI, and Table 35 describes the timing

parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC

Table 34. LPDDR2 and LPDDR3 Read Cycle

Parameter

Symbol

CK = 400 MHz

Unit

Min

Max

LP26

Minimum required DRAM_DATAxx valid window width for LPDDR2

and LPDDR3

—

270

—

DRAM_SDCLKx_P

DRAM_SDCLKx_N

DRAM_SDQSx_P

DRAM_DATAxx

DATA

LP26

(input)

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