ADCMP394/ADCMP395/ADCMP396

Data Sheet

Rev. B | Page 14 of 18

Figure 38. Programmable Sequencing Control Circuit Timing Diagram

When the SEQ signal changes from low to high impedance, the

maximum delay programmable in the circuit. It is recommended

to have the threshold within 10% to 90% of the pull-up voltage.

Calculate the maximum allowable delay by

(17)

The delay of each output is changed by changing the threshold

voltage, V1 to V4, when the comparator changes its output state.

To calculate the voltage thresholds for the comparator, use the

following formulas:























L

PULLUP

1

C

R

t

REF

e

V

V1

1

(18)























L

R

t

REF

e

V

V2

2

1

(19)























L

R

t

REF

e

V

V3

3

1

(20)























L

PULLUP

4

C

R

t

REF

e

V

V4

1

(21)

The threshold voltages can come from a voltage reference or a

voltage divider circuit, as shown in Figure 36.

R1, R2, R3, R4, and R5 using the following formulas:

R5

R4

R3

R2

R1

I

V

R

DIV

REF

DIV













(22)

REF

DIV

V

V1R

R1 

(23)

R1

V

V2R

R2

REF

DIV





(24)

R2

R1

V

V3R

R3

REF

DIV







(25)

R3

R2

R1

V

V4R

R

REF

DIV









4

(26)

(27)

Figure 39. Circuit Configuration for a Mirrored Voltage Sequencer

Figure 39 shows the circuit configuration for a mirrored voltage

sequencer. When SEQ changes from low to high impedance, the

response is similar to Figure 38. When SEQ changes from high

mirrored power-down sequence.

SEQ

OUT4

OUT3

OUT2

OUT1

V1

V2

V3

V4

OUT4

OUT3

OUT2

OUT1

R2

V2

R3

V3

R4

V4

R5

R1

V1

U1

U2

INA+

INA–

INB+

INB–

INA+

INA–

INB+

INB–

SEQ