SSM2518CPZ-R7 datasheet(29/48 Pages) AD

부품명	SSM2518CPZ-R7

상세설명	Digital Input Stereo, 2 W, Class-D Audio Power Amplifier

PDF	48 Pages

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제조업체	AD [Analog Devices]

홈페이지	http://www.analog.com

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29 / 48 page

Datasheet

SSM2518

Rev. B | Page 29 of 48

SERIAL AUDIO INTERFACE CONTROL REGISTER

Address: 0x03, Reset: 0x00, Name: Serial_Interface_Control

Table 16. Bit Descriptions for Serial_Interface_Control

Bits

Bit Name

Settings

Description

Reset

Access

BCLK_GEN

Internal BCLK Generator Enable.

0x0

Bit clock from BCLK pin is used

Internally generated bit clock is used

LRCLK_MODE

LRCLK Shape Selection. Required only for TDM modes.

0x0

50% duty cycle

1-bit pulse

LRCLK_POL

LRCLK Polarity.

0x0

Rising edge (normal)

Falling edge (inverted)

SAI_MSB

Serial Data Bit Order.

0x0

MSB first

LSB first

[3:2]

SLOT_WIDTH

TDM Slot Width. Required only for TDM modes.

0x0

32 BCLK cycles per slot

24 BCLK cycles per slot

16 BCLK cycles per slot

Reserved

BCLK_EDGE

BCLK Active Edge.

0x0

Rising BCLK edge used

Falling BCLK edge used

RESERVED

Reserved.

0x0

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