P89LPC907FD datasheet(46/51 Pages) PHILIPS

46 / 51 page

Philips Semiconductors

P89LPC906/907/908

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 05 — 17 December 2004

46 of 51

9397 750 14467

[1]

Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

[2]

When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to

hold the device in reset at power-up until VDD has reached its speciﬁed level. When system power is removed VDD will fall below the

minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout

detect circuit may be required to hold the device in reset when VDD falls below the minimum speciﬁed operating voltage.

Table 15:

AC characteristics (P89LPC906)

VDD = 3.0 V to 3.6 V, unless otherwise speciﬁed.

Tamb = −40 °Cto+85 °C for industrial, unless otherwise speciﬁed.[1]

Symbol

Parameter

Conditions

Variable clock

fosc =18MHz

Unit

Min

Max

Min

Max

fRCOSC

internal RC oscillator frequency

(nominal f = 7.3728 MHz) trimmed

±1 % at Tamb =25 °C

7.189

7.557

7.189

7.557

MHz

fWDOSC

internal Watchdog oscillator

frequency (nominal f = 400 kHz)

320

520

320

520

kHz

Crystal oscillator

fosc

oscillator frequency

[2] 0

MHz

tCLCL

clock cycle

see Figure 19

--ns

fCLKP

CLKLP active frequency

MHz

Glitch ﬁlter

glitch rejection, P1.5/RST pin

signal acceptance, P1.5/RST pin

125

glitch rejection, any pin except

P1.5/RST

signal acceptance, any pin except

P1.5/RST

External clock

tCHCX

HIGH time

see Figure 19

tCLCL − tCLCX

tCLCX

LOW time

see Figure 19

tCLCL − tCHCX

tCLCH

rise time

see Figure 19

-5

tCHCL

fall time

see Figure 19

-5

Fig 18. Shift register mode timing.

Valid

tXLXL

002aaa425

Set TI

Set RI

tXHQX

tQVXH

tXHDV

tXHDX

Clock

Output Data

Write to SBUF

Input Data

Clear RI

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