PC87383 datasheet(36/77 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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3.11 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION

3.11.1 General Description

The GPIO functional block includes 21 pins,arranged in three 8-bit ports (ports 0, 1 and 2):

Port 0 contains eight GPIOE pins (i.e., GPIO pins with event detection).

Port 1 contains six GPIOE pins and two GPO pins.

Port 2 contains three GPIO pins (i.e., GPIO pins without event detection).

All pins in port 0 and 1 have full event detection capability, enabling them to trigger the assertion of IRQ signals. Pins in port

2 do not have event detection capability. The runtime registers associated with the three ports are arranged in the GPIO

address space as shown in Table 19. The GPIO base address is 16-byte aligned. Address bits 3-0 are used to indicate the

Table 19. Runtime Registers in GPIO Address Space

3.11.2 Implementation

The standard GPIO port with event detection capability (such as port 0, and port 1 bits 0, 1, 4, 5, 6, and 7) has four runtime

registers. Each pin is associated with a GPIO Pin Configuration register that includes seven configuration bits. Port 2 is a

non-standard port that does not support event detection, and therefore differs from the generic model as follows:

It has two runtime registers for basic functionality: GPDO2 and GPDI2. Event detection registers GPEVEN2 and

GPEVST2 are not available.

Only bits 3-0 are implemented in the GPIO Pin Conﬁguration register of port 2. Bits 6-4, associated with the event

detection functionality, are reserved.

Offset

Mnemonic

Port

Type

00h

GPDO0

GPIO Data Out 0

R/W

01h

GPDI0

GPIO Data In 0

02h

GPEVEN0 GPIO Event Enable 0

R/W

03h

GPEVST0 GPIO Event Status 0

R/W1C

04h

GPDO1

GPIO Data Out 1

R/W

05h

GPDI1

GPIO Data In 1

06h

GPEVEN1 GPIO Event Enable 1

R/W

07h

GPEVST1 GPIO Event Status 1

R/W1C

08h

GPDO2

Data Out 2

R/W

09h

GPDI2

Data In 2

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