SC68C752B datasheet(6/49 Pages) PHILIPS

6 / 49 page

SC68C752B_3

Product data sheet

Rev. 03 — 29 November 2005

6 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

R/W

A logic LOW on this pin will transfer the contents of the data bus (D[0:7])

from an external CPU to an internal register that is deﬁned by address

bits A[0:2]. A logic HIGH on this pin will load the contents of an internal

(D[0:7]) for access by an external CPU.

n.c.

12, 25, 29,

14, 20

not connected

OPA, OPB

32, 9

22, 7

User deﬁned outputs. This function is associated with individual

Channel A and Channel B. The state of these pins is deﬁned by the user

through the software settings of MCR[3]. OPA/OPB is a logic 0 when

MCR[3] is set to a logic 1. OPA/OPB is a logic 1 when MCR[3] is set to a

logic 0. The output of these two pins is HIGH after reset.

RESET

Reset (active LOW). This pin will reset the internal registers and all the

outputs. The UART transmitter output and the receiver input will be

disabled during reset time. RESET is an active LOW input.

RIA, RIB

41, 21

Ring Indicator (active LOW). These inputs are associated with

individual UART Channel A and Channel B. A logic 0 on these pins

indicates the modem has received a ringing signal from the telephone

line. A LOW-to-HIGH transition on these input pins generates a modem

status interrupt, if enabled. The state of these inputs is reﬂected in the

Modem Status Register (MSR).

RTSA, RTSB

33, 22

23, 16

Request to Send (active LOW). These outputs are associated with

individual UART Channel A and Channel B. A logic 0 on the RTS pin

indicates the transmitter has data ready and waiting to send. Writing a

logic 1 in the Modem Control Register MCR[1] will set this pin to a

logic 0, indicating data is available. After a reset these pins are set to a

logic 1. These pins only affect the transmit and receive operations when

Auto-RTS function is enabled via the Enhanced Feature Register

(EFR[6]) for hardware ﬂow control operation.

RXA, RXB

5, 4

4, 3

Receive data input. These inputs are associated with individual serial

channel data to the SC68C752B. During the local Loopback mode,

these RX input pins are disabled and TX data is connected to the UART

RX input internally.

RXRDYA,

RXRDYB

31, 18

Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW when

the trigger level has been reached or the FIFO has at least one

character. It goes HIGH when the RX FIFO is empty.

TXA, TXB

7, 8

5, 6

Transmit data A, B. These outputs are associated with individual serial

transmit channel data from the SC68C752B. During the local Loopback

mode, the TX output pin is disabled and TX data is internally connected

to the UART RX input.

TXRDYA,

TXRDYB

43, 6

Transmit Ready (active LOW). TXRDYA or TXRDYB go LOW when

there are at least a trigger level number of spaces available or when the

FIFO is empty. It goes HIGH when the FIFO is full or not empty.

Table 2:

Pin description …continued

Symbol

Type

Description

LQFP48

HVQFN32

SC68C752B 데이터시트(PDF) 6 Page - NXP Semiconductors

SC68C752B 데이터시트(HTML) 6 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

데이터시트 다운로드

링크 URL