FUSB301

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3

PIN DESCRIPTIONS

Pin #

Name

Type

Description

USB Type−C Connector Interface

6, 7

CC1, CC2

I/O

Type−C Configuration Channel

8

VBUS

Input

VBUS input pin for attach and detach detection

4

GND

Ground

Ground

Power Interface

5

VDD

Power

Input Supply Voltage

Signal Interface

1

SDA

Input

2

SCL

Open−Drain

I/O

3

ID

Open−Drain

Output

Used to Identify if connected device is Source to Sink. The ID Pin can

be used to interface with USB 2.0 Input on the processor.

9

SS_SW

CMOS Output

External Super Speed Switch control without processor interrupt.

10

INT_N

Open−Drain

Output

Active Low open drain interrupt output used to prompt processor to

Dead Battery

If power is not applied to FUSB301 and it is attached to

a Source device, then the Source would pull up the CC line

connected through the cable. The FUSB301 in response

would turn on the pull−down that will bring the CC voltage

to a range that the Source can detect an attach and turn on

VBUS.

Power Up, Initialization and Reset, Interrupt Operation

When power is first applied, the FUSB301 will power up

in Sink mode with all interrupts masked. The local processor

must configure the FUSB301 to the desired mode and clear

the global interrupt mask bit, INT_MASK. The INT_N pin

is an active low, open drain output. This pin indicates to the

host processor that an interrupt has occurred in the

FUSB301 which needs attention. The INT_N pin is in a high

impedance state by default after power−up or device reset,

and the global interrupt mask (INT_MASK in Control

register) is set. After INT_MASK bit is cleared by the local

processor, the INT_N pin stays high impedance in

preparation of future interrupts. When an interruptible event

occurs, INT_N is driven LOW and is in a high impedance

state again when the processor clears the interrupt by reading

the interrupt registers. Subsequent to the initial power up or

reset; if the processor writes a “1” to global interrupt mask

bit when the system is already powered up, the INT_N pin

stays in a high impedance state and ignores all interrupts

until the global interrupt mask bit is cleared. If an event

happens that would ordinarily cause an interrupt when the

global interrupt mask bit is set, the INT_N pin goes LOW

when the global interrupt mask is cleared.

SuperSpeed Switch Control

For applications that require a SuperSpeed USB switch

(USB3.1 Gen 1), the SS_SW pin will autonomously control

the USB switch, such as the FUSB340TMX, without

interrupting the processor.

Table 1. SUPERSPEED SWITCH TRUTH TABLE

CC1

CC2

ORIENT1

ORIENT0

SS_SW

Not Connected

Not Connected

0

0

Low

Connected to CC

0

1

Low

Connected to CC

1

0

High

Not Connected

Not Connected

1

1

Low

Table 2. ID PIN TRUTH TABLE

TYPE Register (h12, bit 4)

Description

ID

SINK = b0

SINK Not Detected

Hi−Z (default)

SINK = b1

SINK Detected

Low