AD9528 datasheet(23/67 Pages) AD

부품명	AD9528

상세설명	JESD204B Clock Generator with 14 LVDS/HSTL Outputs

PDF	67 Pages

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23 / 67 page

Data Sheet

AD9528

Rev. D | Page 23 of 67

TYPICAL APPLICATION CIRCUIT

The AD9528 is capable of synchronizing multiple devices

designed to the JESD204B JEDEC standard. Figure 26 illustrates

the AD9528 synchronizing to the system reference clock. The

AD9528 first jitter cleans the system reference clock and

multiples up to a higher frequency in dual loop mode. The

clock distribution of the AD9528 is used to clock and synchronize

all the surrounding JESD204B devices together in the system.

CLOCK

CLEANUP

TRANSCEIVER

CONTROL AND DATA

INTERFACES

TIMING AND

CLOCK

GENERATION

DEVICE

CLOCK

SYSREF

AD9528

OPTIONAL DEVICE CLOCK AND SYSREF PAIRS

FOR OTHER TRANSCEIVERS OR LOGIC DEVICES

DEVICE

CLOCK

SYSREF

SYSTEM

REFERENCE

CLOCK

TO NETWORK

PROCESSOR

BASEBAND

PROCESSOR

ADP5054

ADP5052

DC-TO-DC

CONVERTER

(SWITCHER)

ADP150

ULTRA LOW

NOISE LDO

VCXO

Figure 26. Synchronizing Multiple JESD204B Devices

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