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AD9554BCPZ 데이터시트(PDF) 27 Page - Analog Devices

부품명 AD9554BCPZ
상세설명  Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
PDF  116 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9554BCPZ 데이터시트(HTML) 27 Page - Analog Devices

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Data Sheet
AD9554
Rev. D | Page 27 of 116
WRITE:
REGISTER 0xA00[2] = 0
WRITE:
REGISTER 0x00F = 0x01
CAL_COUNT = 0
CAL_COUNT =
CAL_COUNT + 1
WRITE:
REGISTER 0xA00[2] = 1
WRITE:
REGISTER 0x00F = 0x01
START TIMEOUT CLOCK:
TIME = 0
VCO
CALIBRATION
OPERATION
SYSTEM CLOCK
RECALIBRATION LOOP
SYSTEM CLOCK
LOCKED AND
STABLE POLLING
LOOP
REGISTER
0xD01[1:0] = 0x3
CAL_COUNT > 1
TIMEOUT CLOCK:
TIME > SYSCLK_TO*
YES
YES
YES
NO
NO
NO
START
END
END
(TO RST_COUNT CHECK)
*SYSCLK_TO IS A CALCULATED TIMEOUT VALUE. IT IS 100ms AND SYSTEM CLOCK VALIDATION
TIME (REGISTER 0x206 TO REGISTER 0x208: DEFAULT = 50ms)
Figure 27. Subprocess—System Clock Initialization



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