AM29BDD160G datasheet(22/80 Pages) AMD

22 / 80 page

Am29BDD160G

Burst Access Timing Control

In addition to the IND/WAIT# signal control, burst

controls exist in the Control Register for initial access

delay, delivery of data on the CLK edge, and the

length of time data is held.

Initial Burst Access Delay Control

The Am29BDD160 contains options for initial access

delay of a burst access. The initial access delay has

no effect on asynchronous read operations.

Burst Initial Access Delay is defined as the number of

clock cycles that must elapse from the first valid

clock edge after ADV# assertion (or the rising edge

of ADV#) until the first valid CLK edge when the data

is valid.

The burst access is initiated and the address is

latched on the first rising CLK edge when ADV# is

active or upon a rising ADV# edge, whichever comes

first. (See Table 8 describes the initial access delay

configurations.) If the Clock Configuration bit in the

Control Register is set to falling edge (CR6 = 0), the

definition remains the same for the initial delay set-

ting withe the exception that data is valid after the

falling edge.

Figure 3. Initial Burst Delay Control

Notes:

1. Burst access starts with a rising CLK edge and when ADV# is active.

2. Configurations register 6 is set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.

3. CR [13-10] = 1 or three clock cycles

4. CR [13-10] = 2 or four clock cycles

5. CR [13-10] = 3 or Five clock cycles

Table 8. Burst Initial Access Delay

CR13

CR12

CR11

CR10

Initial Burst Access

(CLK cycles)

54D, 64C, 65A

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