AM29BDD160G datasheet(49/80 Pages) AMD

49 / 80 page

Am29BDD160G

Legend:

BA = Address of the bank that is being switched to autose-

lect mode, is in bypass mode, or is being erased. Deter-

mined by A18 and A17, see Tables 11 and 12 for more

detail.

PA = Program Address (A18:A-1). Addresses latch on the

falling edge of the WE# or CE# pulse, whichever hap-

pens later.

PD = Program Data (DQ15:DQ0) written to location PA.

Data latches on the rising edge of WE# or CE# pulse,

whichever happens first.

RA = Read Address (A18:A-1).

RD = Read Data (DQ15:DQ0) from location RA.

SA = Sector Address (A18:A11) for verifying (in autoselect

mode), erasing, or applying security commands

WD = Write Data. See “Configuration Register” definition for

specific write data. Data latched on rising edge of WE#.

X = Don’t care

Note:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles

are write operations.

4. During unlock cycles, (lower address bits are AAA or

555h as shown in table) address bits higher than A11

Table 21. Memory Array Command Definitions (x16 Mode)

Command (Notes)

Cycles

Bus Cycles (Notes 1–4)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (5)

Reset (6)

XXX

Autoselec

t (7)

Manufactur

er ID

AAA

555

AAA

(BA)X0

Device ID

(11)

AAA

555

AAA

(BA)X0

(BA)X1C

(BA)X1E

00/

Program

AAA

555

AAA

Chip Erase

AAA

555

AAA

555

Sector Erase

AAA

555

AAA

555

Program/Erase

Suspend (12)

Program/Erase Resume

(13)

CFI Query (14, 15)

Accelerated Program

(16)

Configuration Register

Verify (15)

AAA

555

(BA)55

(BA)XX

Configuration Register

Write (17)

AAA

555

AAA

Unlock Bypass Entry

(18)

AAA

555

AAA

Unlock Bypass Program

(18)

Unlock Bypass Erase

(18)

Unlock Bypass CFI (14,

18)

Unlock Bypass Reset

(18)

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