AD5693RARMZ datasheet(5/26 Pages) AD

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Data Sheet

AD5693R/AD5692R/AD5691R/AD5693

Rev. D | Page 5 of 26

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREF = 2.5 V to VDD − 0.2 V, VLOGIC = 1.62 V to 5.5 V, −40°C < TA < +105°C,

typical at 25°C, unless otherwise noted.

Table 3.

Parameter

Typ

Max

Unit

Conditions/Comments

Output Voltage Settling Time1, 2

µs

Gain = 1

Slew Rate

0.7

V/µs

Digital-to-Analog Glitch Impulse1

0.1

nV-s

±1 LSB change around major carry, gain = 2

Digital Feedthrough1

0.1

nV-s

Total Harmonic Distortion1

−80

At ambient temperature, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz

Output Noise Spectral Density1

300

nV/√Hz

DAC code = midscale, 10 kHz

Output Noise

µV p-p

0.1 Hz to 10 Hz; internal reference

SNR

At ambient temperature, bandwidth (BW) = 20 kHz, VDD =5 V, fOUT = 1 kHz

SFDR

At ambient temperature, BW = 20 kHz, VDD =5 V, fOUT = 1 kHz

SINAD

At ambient temperature, BW = 20 kHz, VDD =5 V, fOUT = 1 kHz

See the Terminology section.

For the AD5693R/AD5693, to ±2 LSB. For the AD5692R, to ±1 LSB. For the AD5691R, to ±0.5 LSB

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V, VLOGIC = 1.62 V to 5.5 V, −40°C < TA < +105°C, unless otherwise noted.

Table 4.

Parameter1

Min

Typ

Max

Unit

Description

fSCL2

400

kHz

Serial clock frequency

0.6

µs

SCL high time, tHIGH

1.3

µs

SCL low time, tLOW

100

Data setup time, tSU; DAT

t43

0.9

µs

Data hold time, tHD; DAT

0.6

µs

Setup time for a repeated start condition, tSU; STA

0.6

µs

Hold time (repeated) start condition, tHD; STA

1.3

µs

Bus free time between a stop and a start condition, tBUF

0.6

µs

Setup time for a stop condition, tSU; STO

300

Rise time of SDA signal, tr

t104

20 × (VDD/5.5 V)

300

Fall time of SDA signal, tf

t11

300

Rise time of SCL signal, tr

t124

20 × (VDD/5.5 V)

300

Fall time of SCL signal, tf

tSP5

Pulse width of suppressed spike (not shown in Figure 3)

t13

400

LDAC falling edge to SCL falling edge

t14

400

LDAC pulse width (synchronous mode)

t15

LDAC pulse width (asynchronous mode)

t16

RESET pulse width

tREF_POWER_UP6

600

µs

Reference power-up (not shown in Figure 3)

tSHUTDOWN7

µs

Exit shutdown (not shown in Figure 3)

Maximum bus capacitance is limited to 400 pF. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the

EMC behavior of the device.

The master should add at least 300 ns for the SDA signal (with respect to the VOH (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

Substitute VLOGIC for VDD on devices that include a VLOGIC pin.

Not applicable for standard mode.

Expect the same timing when powering up the device after VDD is equal to 2.7 V.

Time to exit power-down to normal mode of AD5693R/AD5692R/AD5691R/AD5693 operation.

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